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Scoured 72618 posts in 613.9 ms
ANN v3: 200ms p99 query latency over 100 billion vectors
turbopuffer.com·20h·
Discuss: Hacker News
🚀Milvus
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Scalable Adaptive Memory Compiler Optimization via Multi-Objective Evolutionary Algorithms
dev.to·17h·
Discuss: DEV
🧩mimalloc
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Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension
semiwiki.com·1d
📏Picolibc
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SplittingSecrets: A Compiler-Based Defense for Preventing Data Memory-Dependent Prefetcher Side-Channels
arxiv.org·15h
🚀Software Prefetching
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FlashAttention 4: Faster, Memory-Efficient Attention for LLMs
digitalocean.com·8h
🔄Hardware Transactional Memory
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Weird RAM issue
68kmla.org·13h
🔄Memory Disambiguation
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A Novel Side-channel Attack That Utilizes Memory Re-orderings (U. of Washington, Duke, UCSC et al.)
semiengineering.com·1h
🔄Hardware Transactional Memory
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AMD MI455X Could Combine HBM4 And LPDDR For Massive AI Memory Capacity
hothardware.com·1d
💾HBM
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NVIDIA Upgrades "Vera Rubin" Memory Bandwidth Ahead of AMD Instinct MI400 Launch
techpowerup.com·1d
Hardware Acceleration
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A New Way to Debug Query Performance in Cloud Dedicated
influxdata.com·1d
📊Vectorized Query Execution
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Arctic Wolf’s Liquid Clustering Architecture Tuned for Petabyte Scale
databricks.com·2h
🎚️Tiered Storage
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Memory Addressing and Memory Mapped I/O | by Tom Herbert | Jan, 2026
medium.com·2d
🗂️mmap
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If your workload eats memory, this MacBook Pro is the smart configuration
digitaltrends.com·45m
Intel TSX
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AMD Software : Adrenalin Edition 26.1.1
forums.anandtech.com·4h
📊Performance Tools
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Klara’s Expert Perspective on OpenZFS in 2026 and What to Expect Next
klarasystems.com·2h
🎚️Tiered Storage
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PI Introduces Miniaturized Alignment Engine Platform for Scalable, Parallel E/O Wafer-Level Test
prnewswire.com·7h
🧠PIM
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Micron accelerates DRAM expansion through cooperation with Powerchip
igorslab.de·1d
🧠PIM
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Memory layout matters: Reducing metric storage overhead by 4x in a Rust TSDB
baarse.substack.com·5h·
Discuss: r/rust
🏛️Region-Based Memory
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Silicon $T$-center hyperfine structure and memory protection schemes
link.aps.org·16h
🔄Hardware Transactional Memory
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Heaps do lie: debugging a memory leak in vLLM.
mistral.ai·5h·
Discuss: Hacker News
📊Cachegrind
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